Title :
The implementation of a 2-core multi-threaded Itanium®-family processor
Author :
Naffziger, Samuel ; Stackhouse, Blaine ; Grutkowski, Tom
Author_Institution :
Intel, Fort Collins, CO, USA
Abstract :
The next generation in the Itanium® processor family, code named Montecito, is introduced. Implemented in a 90nm 7M process, the processor has two dual-threaded cores integrated with 26.5MB of cache. Of the total of 1.72B transistors, 64M are dedicated to logic and the rest to cache. With both cores operating at full speed, the chip consumes 100W.
Keywords :
cache storage; microprocessor chips; multi-threading; 100 W; 2-core multi-threaded processor; 26.5 MB; 90 nm; Itanium processor family; Montecito; cache; dual-threaded cores; Circuits; Databases; Delay; Energy management; Frequency; Power system management; Program processors; Registers; Switches; Yarn;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493929
