The design and implementation of a first-generation CELL processor

Author

Pham, D. ; Asano, S. ; Bolliger, M. ; Day, M.N. ; Hofstee, H.P. ; Johns, C. ; Kahle, J. ; Kameyama, A. ; Keaty, J. ; Masubuchi, Y. ; Riley, M. ; Shippy, D. ; Stasiak, D. ; Suzuoki, M. ; Wang, M. ; Warnock, J. ; Weitzel, S. ; Wendel, D. ; Yamazaki, T. ; Ya

Author_Institution

IBM Corp., Austin, TX, USA

fYear

2005

Firstpage

184

Abstract

A CELL processor is a multi-core chip consisting of a 64b power architecture processor, multiple streaming processors, a flexible IO interface, and a memory interface controller. This SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high-frequency clock-rate.

Keywords

clocks; controllers; memory architecture; silicon-on-insulator; system-on-chip; 64 bit; 64b power architecture processor; 90 nm; SOI technology; SoC; custom circuit content; first-generation CELL processor; flexible IO interface; high-frequency clock rate; memory interface controller; modularity; multi-core chip; multiple streaming processors; reuse; Clocks; Delay; Frequency; Integrated circuit interconnections; Latches; Linux; Operating systems; Power system interconnection; Repeaters; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-8904-2

Type

conf

DOI

10.1109/ISSCC.2005.1493930

Filename

1493930