DocumentCode :
1670081
Title :
A novel constraint length 13 Viterbi decoder based on the iterative collapse algorithm
Author :
Daneshgaran, F. ; Yao, K. ; Mondin, M.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
fYear :
1992
Firstpage :
1255
Abstract :
The system tradeoff issues of the VLSI design of a single chip constraint length 13 Viterbi decoder (VD) are addressed. All aspects of the design from the feasibility study down to the architecture of the add-compare-select (ACS) units are covered. The unifying thread that guides the development of the design is the iterative collapse algorithm (ICA) for partitioning the trellis diagram in a hierarchical fashion leadin to many diverse topologies for the VD, providing optimal tradeoffs between complexity and throughput. The development breaks down the natural boundaries of architectural tradeoffs and feasibility, memory management, design of the ACS units, and pipelining
Keywords :
VLSI; decoding; digital integrated circuits; iterative methods; ACS units; VLSI design; add-compare-select units; feasibility study; iterative collapse algorithm; pipelining; single chip constraint length 13 Viterbi decoder; system tradeoff issues; Algorithm design and analysis; Independent component analysis; Iterative algorithms; Iterative decoding; Partitioning algorithms; Throughput; Topology; Very large scale integration; Viterbi algorithm; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Global Telecommunications Conference, 1992. Conference Record., GLOBECOM '92. Communication for Global Users., IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-0608-2
Type :
conf
DOI :
10.1109/GLOCOM.1992.276594
Filename :
276594
Link To Document :
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