Title :
Implementation of a 4th-generation 1.8GHz dual-core SPARC V9 microprocessor
Author :
Hart, Jason ; Choe, Swee Yew ; Cheng, Lik ; Chou, Chipai ; Dixit, Anand ; Ho, Kenneth ; Hsu, Jesse ; Lee, Kyung ; Wu, John
Author_Institution :
Sun Microsystems, Sunnyvale, CA, USA
Abstract :
This fourth-generation processor combines two enhanced third-generation cores using an advanced 90nm dual-Vt dual-gate-oxide technology. Hardware additions feature expanded caches and inclusion of a 2 MB level 2 cache and a level 3 tag. The chip operates at 1.8GHz while dissipating <100W at 1.1V.
Keywords :
cache storage; microprocessor chips; 1.1 V; 1.8 GHz; 90 nm; dual-core SPARC V9 microprocessor; dual-gate-oxide technology; enhanced third-generation cores; expanded caches; fourth-generation processor; level 2 cache; level 3 tag; Clocks; Crosstalk; Dielectrics; Flip-flops; Libraries; Microprocessors; Phase locked loops; Repeaters; Sun; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493931
