Title :
A novel technique for noise reduction in CMOS subsamplers
Author :
Lindfors, S. ; Pärssinen, A. ; Ryynänen, J. ; Halonen, K.
Author_Institution :
Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo, Finland
Abstract :
The operation and design aspects of a receiver with a subsampling mixer are discussed at system level. A novel technique that improves the noise performance of CMOS subsamplers is proposed. The sampling frequency with the proposed structure is fundamentally limited by the speed of the clock generator instead of the hold amplifier as is the case in previously reported subsamplers. A 300 MHz test sampler which is designed to be integrated together with a 1.8 GHz LNA is described
Keywords :
CMOS integrated circuits; interference suppression; mixed analogue-digital integrated circuits; mixers (circuits); radio receivers; shift registers; signal sampling; timing; 1.8 GHz; 300 MHz; CMOS subsamplers; LNA; clock generator speed; direct conversion receiver; noise reduction; sampling clock generation; sampling frequency; subsampling mixer; Bandwidth; CMOS technology; Energy consumption; Filters; Frequency; Mixers; Noise figure; Noise reduction; Receivers; Sampling methods;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.704350
