A VLSI architecture for a single-chip 5-Mbaud QAM receiver

The architecture design and VLSI implementation of 5-MBd quadrature amplitude modulation (QAM) receiver chip are discussed. The chip contains all of the signal processing blocks required to implement a complete all-digital QAM receiver including a quadrature demodulator, an adaptive feedforward equalizer (FFE), an adaptive decision-feedback equalizer (DFE), a sampling phase error detector, and a numerically controlled oscillator (NCO). The FFE and DFE are both 20-tap filters and use an LMS coefficient updating algorithm. The FFE can be used in either a T-spaced or T/2-spaced mode. The projected maximum clock frequency of the receiver chip is 100 MHz for a symbol rate of 5 MBd. The receiver accommodates modulation formats as complex as 256-QAM, which corresponds to a peak throughput rate of 40 Mb/s. The chip will be fabricated in 1.0-μm CMOS, and will require an estimated 10-mm×7-mm die area