A 50 Mvertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

Author

Sohn, Ju-Ho ; Woo, Jeong-Ho ; Lee, Min-Wuk ; Kim, Hye-Jung ; Woo, Ramchan ; Yoo, Hoi-Jun

Author_Institution

KAIST, Daejeon, South Korea

fYear

2005

Firstpage

192

Abstract

A user-programmable mobile 3D graphics processor with a 32 bit RISC, a 128 bit fixed-point SIMD vertex shader and a rendering engine is implemented. A programmable frequency synthesizer controls the clock frequency continuously and adaptively for low power. The chip achieves 50 Mvertices/s and 200 Mtexels/s, dissipating 155 mW in a 0.1 μm 6M CMOS process.

Keywords

CMOS digital integrated circuits; coprocessors; frequency synthesizers; low-power electronics; power consumption; reduced instruction set computing; rendering (computer graphics); 0.18 micron; 128 bit; 155 mW; 32 bit; CMOS process; RISC; SIMD vertex shader; clock frequency; fixed-point programmable vertex shader; fixed-point vertex shader; low power; mobile 3D graphics processor; power consumption; programmable frequency synthesizer; rendering engine; Coprocessors; Energy consumption; Engines; Frequency synthesizers; Graphics; Hardware; Random access memory; Reduced instruction set computing; Registers; Rendering (computer graphics);

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-8904-2

Type

conf

DOI

10.1109/ISSCC.2005.1493934

Filename

1493934