Title :
A 51.2 GOPS 1.0 GB/s-DMA single-chip multi-processor integrating quadruple 8-way VLIW processors
Author :
Shiota, Tetsuyoshi ; Kawasaki, Ken-Ichi ; Kawabe, Yukihito ; Shibamoto, Wataru ; Sato, Atsushi ; Hashimoto, Tetsutaro ; Hayakawa, Fumihiko ; Tago, Shin-Ichirou ; Okano, Hiroshi ; Nakamura, Yasuki ; Miyake, Hideo ; Suga, Atsuhiro ; Takahashi, Hiromasa
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
A 51.2-GOPS chip multi-processor integrates four 8-way VLIW embedded processors with 1.0 GB/s local-bus direct memory access. This IC completes MPEG2 MP@HL video-stream decoding at 68% of its processor capability without dedicated hardware. The 11.9 mm × 10.3 mm chip is fabricated in a 90 nm 9M CMOS process and consumes 5 W at 533 MHz.
Keywords :
CMOS digital integrated circuits; decoding; embedded systems; file organisation; microprocessor chips; multiprocessing systems; parallel architectures; power consumption; video coding; 1.0 GB/s; 11.9 to 10.3 mm; 5 W; 533 MHz; 90 nm; CMOS process; DMA; MPEG2 video-stream decoding; VLIW processors; embedded processors; local-bus direct memory access; parallel operations; single-chip multiprocessor; Bandwidth; Circuit noise; Clocks; Decoding; Hardware; Multiaccess communication; Packaging; Printers; Random access memory; VLIW;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493935
