Title :
A SOI capacitor-less 1T-DRAM concept
Author :
Okhonin, S. ; Nagoga, M. ; Sallese, J.M. ; Fazan, P.
Author_Institution :
LEG, Swiss Fed. Inst. of Technol., Lausanne, Switzerland
Abstract :
A simple 1T DRAM cell concept is proposed for the first time. It exploits the body charging of PD SOI devices to store the information. This cell is at least two times smaller in area than the conventional 1T/1C DRAM cell and does not require the integration of a storage capacitor. This concept should allow the manufacture of low cost DRAMs and eDRAMs for 100 and sub 100 nm generations.
Keywords :
DRAM chips; elemental semiconductors; integrated circuit design; nanotechnology; silicon; silicon-on-insulator; 1 Tbit; 100 nm; PD SOI; SOI capacitor-less 1T-DRAM; Si-SiO/sub 2/; body charging; eDRAMs; low cost DRAMs; manufacture; Analytical models; Bipolar transistors; CMOS technology; Capacitors; Impact ionization; Leg; MOSFET circuits; Manufacturing; Random access memory; Voltage;
Conference_Titel :
SOI Conference, 2001 IEEE International
Conference_Location :
Durango, CO, USA
Print_ISBN :
0-7803-6739-1
DOI :
10.1109/SOIC.2001.958032
