Design approach for a Low Power video decoder

Author

Melcher, Elmar U K ; Cunha, Henrique N. ; Nascimento, Maria L. ; Melo, Fabricio G L ; Rodrigues, Matheus B E

Author_Institution

Center of Electr. Eng. & Comput., Campina Grande, Brazil

fYear

2009

Firstpage

231

Lastpage

234

Abstract

This paper presents a detailed description of the design of a Low Power, SystemC-RTL, OCP-IP compliant MPEG-4 decoder IP-core, named Terpsicore. The Terpsicore was designed for use in embedded systems where low cost, high performance and power efficiency are important. This design supports simple profile L0 with two external memories, was manufactured using a 0.35um CMOS 4ML technology and has a die of 49mm² comprising 48095 gates. It consumes 115mW at 25MHz when video encoding of QCIF at 15fps with a voltage supply of 3.3V. Compared with other implementations of the MPEG-4 standard available in the market, the Terpsicore presents better energy efficiency and this paper shows how this was achieved.

Keywords

CMOS integrated circuits; low-power electronics; video codecs; video coding; CMOS 4ML technology; OCP-IP compliant MPEG-4 decoder IP-core; SystemC-RTL; Terpsicore; energy efficiency; frequency 25 MHz; low power video decoder; power 115 mW; size 0.35 mum; voltage 3.3 V; CMOS integrated circuits; CMOS technology; Decoding; Embedded systems; Encoding; Logic gates; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Very Large Scale Integration (VLSI-SoC), 2009 17th IFIP International Conference on

Conference_Location

Florianopolis

Print_ISBN

978-1-4577-0237-2

Type

conf

DOI

10.1109/VLSISOC.2009.6041363

Filename

6041363