Improving wafer fabrication performance by Hierarchical colored timed Petri-net and SA - based approach

The paper describes an approach to scheduling for semiconductor wafer fabrication. In order to effectively analyze of control for semiconductor wafer fabrication, a Hierarchical colored timed Petri net (HCTPN) modeling technology based on the comprehensive analysis of the semiconductor manufacturing process was proposed. Due to the wide acceptance of priority rules in the wafer fabrication, we proposed a simulated annealing (SA) to search for the optimal combination of a number of priority rules in the HCTPN models. Computational results are presented that our approach constantly generates better solutions compared to those obtained by commonly- used dispatching rules.