Power gradient based Design Space Exploration in high level synthesis for DSP kernels

Design Space Exploration (DSE) of integrated scheduling and module selection in high level synthesis for VLSI applications require an accurate optimization technique capable of reaching an optimal/near-optimal solution rapidly. This paper introduces a novel heuristic based multi objective optimization (exploration) process based on power gradient theory that simultaneously reduces the static power consumption at the usage of minimal control step (time step) during scheduling. The proposed iterative power aware integrated optimization approach is based on Priority Indicator (PI) function which is responsible for minimizing allocated hardware functional units during the scheduling process. The quality of final solution obtained by the proposed approach has been compared to a heuristic Genetic Algorithm (GA) based approach. Results for the benchmarks indicate an average power reduction of 11%, improvement in the quality of final solution of 5.07% and reduction in optimization/exploration runtime of 59%.