Title :
A 3.3 mW 12 MS/s 10b pipelined ADC in 90 nm digital CMOS
Author :
Wang, Robert ; Martin, Ken ; Johns, David ; Burra, Gangadhar
Author_Institution :
Univ. of Toronto, Ont., Canada
Abstract :
A 10b pipelined ADC has been realized in a digital 90 nm CMOS technology using techniques such as switched opamps and switched-input buffers. Measurements show that this ADC samples at 12 MS/s achieving a peak SNDR of 52.6 dB using a 1.2 V supply. It consumes 3.3 mW and occupies 0.3 mm2 core area.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; buffer circuits; integrated circuit design; integrated circuit measurement; low-power electronics; operational amplifiers; switched networks; 1.2 V; 10 bit; 3.3 mW; 90 nm; ADC sampling rate; core area; digital CMOS pipelined ADC; peak SNDR; power consumption; switched opamps; switched-input buffers; Error correction; Frequency; Operational amplifiers; Power supplies; Sampling methods; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1493977
