• DocumentCode
    1671244
  • Title

    A 10 b 125 MS/s 40 mW pipelined ADC in 0.18 μm CMOS

  • Author

    Yoshioka, Masato ; Kudo, Masahiro ; Gotoh, Kunihiko ; Watanabe, Yuu

  • Author_Institution
    Fujitsu Labs. Ltd., Kawasaki, Japan
  • fYear
    2005
  • Firstpage
    282
  • Abstract
    A 10 b 125 MS/s pipelined ADC uses a new front-end circuit and consumes 40 mW from a 1.8 V supply. The ADC is implemented in a 0.18 μm CMOS process and has an active area of 1.1×0.6 mm2. Measured INL (integral nonlinearity) and DNL (differential nonlinearity) are within ±0.7 LSB, and ±0.5 LSB, respectively. Peak SNDR is 53.7 dB with a 2 MHz input.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; integrated circuit design; power consumption; 0.18 micron; 0.6 mm; 1.1 mm; 1.8 V; 2 MHz; 40 mW; CMOS process; differential nonlinearity; front-end circuit; integral nonlinearity; pipelined ADC; power consumption; Capacitors; Consumer products; Energy consumption; High power amplifiers; Laboratories; Pipelines; Power amplifiers; Power supplies; Voltage; Wireless communication;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1493979
  • Filename
    1493979
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1671244