Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs

Author

Nose, Koichi ; Shibayama, Atsufumi ; Kodama, Hiroshi ; Mizuno, Masayuki ; Edahiro, Masato ; Nishi, Naoki

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

2005

Firstpage

296

Abstract

Periodically all-in-phase clocking (8-step frequency increments with a 4.5 ns switching time) and deterministic synchronous bus wrappers (synchronized data transfer among different frequency cores) are developed for dynamic voltage- and frequency-scaling multi-core SoCs. A maximum of 60% power reduction in MPEG-4 decoding with 1.5 to 2× throughput increase are confirmed.

Keywords

low-power electronics; signal generators; synchronisation; system-on-chip; video coding; 4.5 ns; MPEG-4 decoding power reduction; clock distribution network; clock generator; deterministic inter-core synchronization; deterministic synchronous bus wrapper; differing frequency cores; dynamic frequency-scaling; dynamic voltage scaling; low-power multicore SoC; periodically all-in-phase clocking; synchronized data transfer; Asynchronous communication; Clocks; Data communication; Digital signal processing; Frequency synchronization; National electric code; Nose; Synchronous generators; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-8904-2

Type

conf

DOI

10.1109/ISSCC.2005.1493986

Filename

1493986