Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm CMOS

Local voltage dithering combined with sub-threshold operation permits ultra-dynamic voltage scaling from 1.1 V to below 300 mV for a 90 nm CMOS adder test chip. Operating at 330 mV, it provides minimum energy per cycle with 9-times less energy than ideal shutdown for reduced-rate scenarios. Measurements characterize the minimum energy point across temperature.