High-resolution digital PWM controller for high-frequency low-power SMPS

This paper proposes a high-resolution Digital-PWM (DPWM) architecture for high-frequency low-power Switching Mode Power Supply (SMPS). The proposed DPWM takes advantage of Digital Clock Manager (DCM) phase-shift characteristics available in FPGA, and combines a counter-comparator with a Multi-stAge-noise-SHaping (MASH) Delta-Sigma (Delta-Sigma) modulator. An 11-bit effective prototype DPWM along with a digital PID control algorithm are experimentally verified by using a Virtex-II FPGA on a discrete low-power buck converter. Experimental results with constant switching frequency up to 4 MHz validate the functionality of the proposed DPWM. In addition, the digital controller is implemented in a 0.35 mum standard CMOS.