Title :
Implementation of a 6.5 MHz 34-B NCO [numerically controlled oscillator]
Author :
Yunhua, Shi ; Shimin, Sheng ; Yue, Liu ; Lijiu, Ji
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
An numerically controlled oscillator chip, using a pipelined structure, has been developed in standard 2 μm P-well CMOS technology. The typical maximum input clock rate is 6.5 MHz. By analysis, the speed limiting factors improved are the delay of the accumulator and the data acquiring rate of the ROM. Through the use of an improved pipelined structure and N-well CMOS technology, an NCO device with a clock rate in excess of 10 MHz is indeed possible
Keywords :
CMOS analogue integrated circuits; CMOS digital integrated circuits; numerical control; pipeline processing; variable-frequency oscillators; 34 bit; 6.5 MHz; P-well CMOS technology; clock rate; numerically controlled oscillator chip; pipelined structure; Circuits; Clocks; Communication system control; Control systems; Filters; Frequency; Read only memory; Tuning; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.500067
