• DocumentCode
    1672189
  • Title

    Testability design for sequential circuit with multiple feedback

  • Author

    Ye, Bo ; Zheng, Zengyu ; Hu, Jun ; Li, Wei

  • Author_Institution
    Dept. of Electron. Eng., Fudan Univ., Shanghai, China
  • fYear
    1995
  • Firstpage
    208
  • Lastpage
    210
  • Abstract
    Partial scan testability design method for sequential circuits with multiple feedback is proposed in this paper. The selection of flip-flops is aimed at breaking up the cyclic structure and reducing the sequential depth of the circuit so that test generation can be simplified. Combinational test generation algorithm is used in this method and it can reach ideal fault coverage. Experimental results show that above 90% fault coverage can be obtained by scanning just 20-40% of the flip-flops
  • Keywords
    circuit feedback; design for testability; flip-flops; logic testing; sequential circuits; combinational test generation algorithm; fault coverage; flip-flops; multiple feedback; partial scan testability design; sequential circuit; Circuit faults; Circuit testing; Circuit topology; Clouds; Feedback circuits; Flip-flops; Logic testing; Sequential analysis; Sequential circuits; State feedback;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
  • Conference_Location
    Beijing
  • Print_ISBN
    0-7803-3062-5
  • Type

    conf

  • DOI
    10.1109/ICSICT.1995.500068
  • Filename
    500068
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1672189