Title :
SE5 - SRAM design in the nanoscale era
Author :
Natarajan, Sreedhar ; Shubat, Alex
Keywords :
Circuit testing; Error analysis; Geometry; Leakage current; Logic devices; Logic testing; Paper technology; Random access memory; Solid state circuit design; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494021
