Power-Gating Adiabatic Flip-Flops and Sequential Logic Circuits

In this paper, adiabatic flip-flops with data-retention function are proposed, and a power-gating scheme for adiabatic sequential circuits is presented. The proposed data-retention flip-flops are realized using CPAL (complementary pass-transistor adiabatic logic) circuits. The active enable and refresh enable terminals are added for the power-gating operation of the flip-flops. The flip-flops work in three modes. In active mode, the flip-flops act as usual. In hold mode, the flip-flops hold their state on the internal nodes. In refresh mode, the internal nodes are refreshed with their storage value by enabling power-clocks. The energy dissipation of power-gating adiabatic sequential circuits is investigated for different frequencies using a 10times10 adiabatic counter. SPICE simulations show that energy loss of the adiabatic sequential circuits is reduced greatly by using power-gating techniques.