Implementation of 2D-DCT on XC4000 series FPGA using DFT-based DSFG and DA architectures

In many multimedia applications, image processing tools require very high speed implementation of the two-dimensional (2D) discrete cosine transform (DCT). Two 2D-DCT architectures were realized based on the decomposition of 2D-DCT into two one-dimensional (1D) DCT. Each of the resultant 1D-DCT was implemented using a flow-graph (FG) representation of the real part of the Fourier transform for the first architecture and the distributed arithmetic (DA) for the second architecture, respectively. Error simulation was performed for different data word lengths, and average and maximum absolute errors were calculated for both architectures for several possible worst cases. Based on the simulation results, the correct word sizes were determined for both implementations. By describing the FG architecture in VHDL and implementing it in the Xilinx XC4000 series FPGA chip, our results showed that the proposed technique utilized less combinational logic blocks (CLB) as compared to the FG realization in Kumar et al., (1999), and at the same time provided performance increase of up to 28% (190 Mpix/sec)