TLP Characterization and Leakage-Biasing-Voltage (VLB) Correlations in MOSFET Measurements

An investigation of leakage-biasing-voltage (V_LB) influence on the final measurement data of TLP testing is proposed in this work. In order to identify the impact on electrostatic discharge (ESD) immunity evaluation, three kinds of MOSFET DUTs are used, which are the LVnMOS (5-V/0.6-um), HVnMOS and HVpMOS (12-V/0.6-um) technologies devices, respectively. After a series of systematic TLP measurement, it can be found that the above mentioned variable (V_LB) has a very serious repercussion on I_t2 values of LVnMOS and HVnMOS, but the influence on HVpMOS DUT is very minor. In terms of device measured I_t2 data, the error of experimental results here caused by a maximum leakage-biasing-voltage (V_LB) is up to 56% in LVnMOS DUTs, 81% in HVnMOS DUTs, and only 5% in HVpMOS DUTs, respectively. Therefore, it will result in many TLP test results of DUTs as compared to their HBM testing data with a considerable deviation. Then, in order to let the real TLP measured values have a good correlation with HBM´s robustness on the same DUT, this setting parameter (V_LB) should be taken into account during the TLP measurement. It is shown that lack of correlation is caused by misinterpretations in the test results, due to the fact that soft and hard failure in a DUT. That is to measure a true I_t2 value of DUTs, a leakage-biasing-voltage (V_LB) state in the TLP testing should not be too high.