Title :
The multi-threaded, parity-protected 128-word register files on a dual-core Itanium®-family processor
Author :
Fetzer, Eric S. ; Wang, Lei ; Jones, Jared
Author_Institution :
Intel, Fort Collins, CO, USA
Abstract :
The dual-thread 18-port 128w×82b FPU register file, and the 22-port 128w×65b integer register file of the microprocessor is described. Parity embedded into each register provides soft error detection. The design integrates a charge-compensated thread switch and power-saving features to operate at 1.1V consuming 400mW at maximum frequency.
Keywords :
error detection; floating point arithmetic; microprocessor chips; multi-threading; 1.1 V; 128-word register files; 400 mW; FPU register file; charge-compensated thread switch; dual-core Itanium-family processor; microprocessor; multi-threaded register files; parity; parity-protected register files; power-saving features; soft error detection; Circuits; Clocks; Logic; Protection; Radio frequency; Registers; Switches; Timing; Voltage; Yarn;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494029
