Title :
A 32b 64-word 9-read-port/7-write-port pseudo dual-bank register file using copied memory cells for a multi-threaded processor
Author :
Sumita, Masaya ; Ikeda, Yuuichirou
Author_Institution :
Matsushita, Nagaokakyo, Japan
Abstract :
A method for copying memory cells to reduce the size of the register file for a multi-threaded processor is proposed. The number of transistors in the memory cell is reduced to 70% and the total bit and word lines is reduced to 63%. The register file is implemented in a 100nm CMOS process. The size of the register file is reduced to 62% of a conventional register file. The power consumption is reduced by 50%.
Keywords :
CMOS memory circuits; microprocessor chips; multi-threading; power consumption; 100 nm; 32 bit; 64-word pseudo dual-bank register file; 9-read-port/7-write-port register file; CMOS process; copied memory cells; multi-threaded processor; power consumption; Circuits; Energy consumption; Latches; Rails; Registers; Signal generators;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494030
