DocumentCode :
1672568
Title :
A 3Gb/s/ch transceiver for RC-limited on-chip interconnects
Author :
Schinkel, Daniël ; Mensink, Eisse ; Klumperink, Eric ; Van Tuijl, Ed ; Nauta, Bram
Author_Institution :
Twente Univ., Enschede, Netherlands
fYear :
2005
Firstpage :
386
Abstract :
A bus-transceiver chip in 0.13 μm CMOS uses 10mm uninterrupted differential interconnects of 0.8 μm pitch (82MHz RC-limited bandwidth). The chip achieves 3Gb/s/ch using a pulse-width pre-emphasis technique in combination with resistive termination while twisted interconnects mitigate crosstalk. Power consumption is 6mW/ch at a 1.2V supply.
Keywords :
CMOS integrated circuits; crosstalk; integrated circuit interconnections; transceivers; 0.13 micron; 1.2 V; 3 Gbit/s; 6 mW; 82 MHz; CMOS; RC-limited on-chip interconnects; bus-transceiver chip; crosstalk; power consumption; pulse-width pre-emphasis; resistive termination; twisted interconnects; uninterrupted differential interconnects; Bandwidth; Clocks; Copper; Integrated circuit interconnections; Power system interconnection; Power system reliability; System-on-a-chip; Transceivers; Transmitters; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
0-7803-8904-2
Type :
conf
DOI :
10.1109/ISSCC.2005.1494031
Filename :
1494031
Link To Document :
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