Title :
0.94ps-rms-jitter 0.016mm2 2.5GHz multi-phase generator PLL with 360° digitally programmable phase shift for 10Gb/s serial links
Author :
Toifl, Thomas ; Menolfi, Christian ; Buchmann, Peter ; Kossel, Marcel ; Morf, Thomas ; Reutemann, Robert ; Ruegg, Michael ; Schmatz, Martin ; Weiss, Jonas
Author_Institution :
IBM, Rueschlikon, Switzerland
Abstract :
A PLL generates 8 equidistant clock phases whose timing with respect to a reference clock can be simultaneously shifted in 3ps steps by a digital value. Each VCO phase is fed to a dedicated phase detector and the weighted detector outputs are summed. Fabricated in 90nm SOI-CMOS technology, the PLL has a jitter of 0.94psrms at 2.5GHz and consumes 20mW from a 0.9V supply.
Keywords :
CMOS integrated circuits; phase detectors; phase locked loops; silicon-on-insulator; timing jitter; voltage-controlled oscillators; 0.9 V; 10 Gbit/s; 2.5 GHz; 20 mW; 90 nm; SOI-CMOS technology; VCO phase; digitally programmable phase shift; equidistant clock phases; jitter; multi-phase generator PLL; phase detector; serial links; timing; weighted detector output summing; Aggregates; Bandwidth; Clocks; Detectors; Energy consumption; Phase detection; Phase locked loops; Ring oscillators; Sampling methods; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494043
