DocumentCode :
1672847
Title :
RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks
Author :
Guha, Krishnendu ; Saha, Debasri ; Chakrabarti, Amlan
Author_Institution :
A.K. Choudhury Sch. of I.T., Univ. of Calcutta, Kolkata, India
fYear :
2015
Firstpage :
1
Lastpage :
6
Abstract :
With the entry into the embedded domain, security of SOC architectures has become an arena of importance. However, complexity and cost factors have forced us to outsource the VLSI design phases across the globe. Such sites may not be trusted and threat lies in the introduction of malicious intrusions at any stage of the design flow. Such malicious intrusions, also known as Hardware Trojan Horses (HTH) remain dormant during the testing phase but get triggered at runtime and threaten the integrity and confidentiality of the chip. In this paper, we focus on threat to confidentiality. HTH threatens the confidentiality of such chips by leaking the secret information at runtime. We propose an intelligent architecture, Runtime Trust Neural Architecture (RTNA) based on Adaptive Resonance Theory (ART 1) neural network, which when incorporated with the SOC architecture can prevent it at runtime from being compromised confidentially. Low area and low power overhead of our proposed RTNA on practical crypto SOC architectures as obtained in the experimental results confirm its practical implementation. Hardware implementation of trust generation at runtime, use of unsupervised learning and use of an intelligent architecture are the novelties of this work.
Keywords :
ART neural nets; VLSI; cryptography; integrated circuit design; invasive software; low-power electronics; system-on-chip; unsupervised learning; ART1 neural networks; HTH; RTNA; VLSI design phases; adaptive resonance theory; confidentiality attacks; cost factors; cryptoSOC architectures; hardware Trojan horses; intelligent architecture; low power overhead; malicious intrusions; runtime trust neural architecture; trust generation; unsupervised learning; Computer architecture; Cryptography; Delays; Hardware; Runtime; System-on-chip; Trojan horses; Adaptive Resonance Theory (ART); Cryptocores; Hardware Trojan Horses (HTH);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
Type :
conf
DOI :
10.1109/ISVDAT.2015.7208048
Filename :
7208048
Link To Document :
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