DocumentCode
1672943
Title
A 1-V 2GHz VLSI CMOS low noise amplifier
Author
Taris, Thieny ; Begueret, Jean Baptiste ; Lapuyade, Hewe ; Deval, Yann
Author_Institution
IXL Lab., Univ. of Bordeaux, Talence, France
fYear
2003
Firstpage
123
Lastpage
126
Abstract
A new LNA topology is presented in this paper. Compatible with VLSI technology the architecture is dedicated to the UMTS third generation mobile phone. Operating under 1 V supply voltage the circuit provides a more than 11 dB gain at 2.1 GHz. With a -11 dBm ICP1, the power consumption is lower than 4 mW, making the architecture well suited to very low power applications. The noise figure of 1.8 dB takes advantage of the inductive degeneration technique. The 0 dBm IIP3 fulfils the UMTS requirement whose the circuit is dedicated to.
Keywords
CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; VLSI; integrated circuit noise; low-power electronics; 1 V; 1.8 dB; 11 dB; 2 GHz; 4 mW; ICP1; IIP3; UMTS third generation mobile phone; VLSI CMOS low noise amplifier; circuit topology; inductive degeneration; low power operation; noise figure; 3G mobile communication; CMOS technology; Circuit noise; Circuit topology; Energy consumption; Gain; Low-noise amplifiers; Mobile handsets; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
ISSN
1529-2517
Print_ISBN
0-7803-7694-3
Type
conf
DOI
10.1109/RFIC.2003.1213908
Filename
1213908
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