Modeling the Impact of Input-to-Output Coupling Capacitance on Power Dissipation Estimation in Deep Submicron CMOS Circuits

In this paper modeling the impact of input-to-output coupling capacitance on power dissipation estimation in submicron CMOS circuits is proposed. Compared with conventional methods, the proposed model is much accurate because it considers the impact of the input-to-output capacitance on power dissipation estimation. In addition, the proposed model can estimate the impact of coupling capacitance on serial gates. The experimental results show that the proposed model can obtain an considerable improvement in accuracy.