High speed self biased current sense amplifier for low power CMOS SRAM´s

Sense amplifiers are one of the important circuits in the CMOS memories as they have a greater impact on the access time and power dissipation of memory cells. The current-mode sense amplifiers have improved the access time as well as power dissipation to a large extent when compared to voltage-mode sense amplifiers, thus resulting in making the memories compatible with the high speed CMOS technologies. In this paper, a new topology of current-mode sense amplifiers is introduced which overcomes the imperfections associated with the conveyer based current-mode sense amplifiers. The circuit has resulted in a low sense delay of 596.6 psecs and power dissipation of 0.87uW and in the end the effect of bit-line capacitances on sense delay, power supply and temperature on power dissipation is calculated.