A novel dual multiplier floating point multiply accumulate architecture

Floating point multiply-accumulate (FPMAC) block is a key unit determining the frequency, power and area of microprocessors. FPMAC unit is used in engineering and scientific applications. In this work we have proposed a novel FPMAC architecture which focuses on optimal computations to make it the fastest FPMAC as of today in literature. Innovations to create a novel Single Precision Dual Multiplier FPMAC (DM-FPMAC) to reduce the timing such as i) Splitting near and far difference based on the exponent difference (d1(Near difference)=E_g - E_m and d2(Far difference) = E_g - E_l), ii) Early shifting of near difference in the LZA/LZO, iii) Combined round and Post-normalization, iv) 3-operand Adder for accumulation. Our design by premise of splitting path consumes lesser power for each operation where only the required logic for each case is switching. The implementation results show that the proposed DM-FPMAC has reduced delay with respect to 2-cycle Lang, Bruguera and Split path FPMAC by 49.06%, 43.39% and 38.63% respectively. The power is reduced with respect to 2-cycle Lang and Bruguera FPMAC by 19.37% and 41.32% respectively. Proposed architecture is realized in Xilinx 14.5 ISE and synthesized using Synopsys Design Compilier with 90nm standard cell library.