• DocumentCode
    1673215
  • Title

    A bit-serial architecture for VLSI Viterbi processor

  • Author

    Bree, Michael A. ; Dodds, David E.

  • Author_Institution
    Saskatchewan Univ., Saskatoon, Sask., Canada
  • fYear
    1988
  • Firstpage
    72
  • Lastpage
    77
  • Abstract
    Viterbi decoding complexity has limited constraint lengths to K=7 and less in fixed constraint length systems. The architecture of a bit-serial Viterbi processor chip that can be used to implement expandable-constraint-length decoders is detailed. Its operation is based on modeling the trellis diagram. This chip can operate with codes of rate 1/2 or 1/3 at data rates in the 100 to 200 kb/s range
  • Keywords
    VLSI; codes; decoding; microprocessor chips; 100 to 200 kbit/s; VLSI Viterbi processor; bit-serial architecture; codes; constraint lengths; decoding complexity; expandable-constraint-length decoders; fixed constraint length systems; processor chip; trellis diagram; Convolutional codes; Decoding; History; Particle measurements; Shift registers; Very large scale integration; Viterbi algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    WESCANEX 88: 'Digital Communications Conference Proceedings'
  • Conference_Location
    Saskatoon, Sask.
  • Type

    conf

  • DOI
    10.1109/WESCAN.1988.27671
  • Filename
    27671
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1673215