A novel approach to reusable time-economized STIL based pattern development

State of the art automotive microcontrollers (MCUs) implementing complex system-on-chip (SoC) architectures requires often additional functional patterns to achieve high degree of reliability. Functional pattern family includes test patterns checking internal device functionality under nominal condition. The development of these patterns is required to augment structural tests to achieve high test coverage. Moreover, it should be planned to minimize test time since it has direct impact on time to market. This paper proposes a reusable and time-economized approach for functional test pattern development using Test Information Model (TIM) discussed in the paper. The flow is also automated to exclude the potential source of error in the pattern generation. In applying this methodology, there is approximately 60%-70% reduction in pattern development time as compared to conventional simulation based pattern development. Also, the results show the efficiency of this approach in terms of pattern reusability by further reducing man-hours of the test engineer.