DocumentCode
1673328
Title
A 16mW, 2.23-2.45GHz fully integrated ΣΔ PLL with novel prescaler and loop filter in 0.35μm CMOS
Author
Shu, Keliu ; Sanchez-Sinencio, Edgar ; Silva-Martinez, Jose ; Embabi, Sherif H K
Author_Institution
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
fYear
2003
Firstpage
181
Lastpage
184
Abstract
A 3mW inherently glitch-free phase-switching prescaler and a loop filter with a 0.2mW capacitance multiplier are proposed for a ΣΔ PLL synthesizer in 0.35μm CMOS. The ΣΔ noise folding is minimized by optimal design of ΣΔ modulator and minimized PLL nonlinearities. The synthesizer has a 9.4% tuning range of 2.23-2.45GHz. The phase noise is -90dBc/Hz at 10kHz, and -128dBc/Hz at 10MHz offset.
Keywords
CMOS integrated circuits; UHF filters; UHF integrated circuits; circuit tuning; frequency synthesizers; phase locked loops; phase noise; prescalers; sigma-delta modulation; 0.35 micron; 16 mW; 2.23 to 2.45 GHz; CMOS ΣΔ PLL frequency synthesizer; capacitance multiplier; loop filter; noise folding; phase noise; phase-switching prescaler; tuning range; Acoustical engineering; Capacitance; Capacitors; Filters; Frequency; Logic; Phase locked loops; Robustness; Switching circuits; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
ISSN
1529-2517
Print_ISBN
0-7803-7694-3
Type
conf
DOI
10.1109/RFIC.2003.1213921
Filename
1213921
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