Title :
An 18.5ns 128MB SOI DRAM with a floating body cell
Author :
Ohsawa, Takashi ; Fujita, Katsuyuki ; Hatsuda, Kosuke ; Higashi, Tomoki ; Morikado, Mutsuo ; Minami, Yoshihiro ; Shino, Tomoaki ; Nakajima, Hiroomi ; Inoh, Kazumi ; Hamamoto, Takeshi ; Watanabe, Shigeyoshi
Author_Institution :
Toshiba Corp., Yokohama, Japan
Abstract :
A dynamic latch sense amplifier/bit line replenishes "1" cells with holes lost during word line cycles and reduces the refresh busy rate. A multi-averaging method of dummy cells over 128 pairs of "1s" and "0s" enhances the sense margin and contributes to the 18.5ns access time. The 25.7ns virtually static RAM (VSRAM) mode is realized by taking advantage of the cell\´s quasi non-destructive read-out.
Keywords :
DRAM chips; amplifiers; flip-flops; nondestructive readout; silicon-on-insulator; 128 MB; 18.5 ns; 25.7 ns; SOI DRAM; VSRAM; bit line; dummy cells; dynamic latch sense amplifier; floating body cell; multi-averaging method; quasi nondestructive read-out; refresh busy rate; virtually static RAM; word line cycles; Charge pumps; Circuit simulation; Displays; Latches; Mirrors; Random access memory; Switches; Voltage; Writing;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494067
