C2-DLM: Cache coherence aware dual link mesh for on-chip interconnect

Throughput-sensitive server workloads are expected to handle voluminous independent and concurrent transactions that require careful designing of an on chip interconnect. State of the art applications take in a very high and even unbounded working sets with concurrent data. It demands for suitable architectural changes for on chip interconnect to maintain the performance of concurrent applications. In this paper, we have proposed a novel dual link mesh on chip interconnect to classify cache traffic for cache coherence MESI directory protocol.