Title :
A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply
Author :
Zhang, K. ; Bhattacharya, U. ; Chen, Z. ; Hamzaoglu, F. ; Murray, D. ; Vallepalli, N. ; Wang, Y. ; Zheng, B. ; Bohr, M.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
A 70MB SRAM chip is designed and fabricated in 65nm CMOS technology. A column-based dynamic multi-V, scheme is integrated into the design to improve cell read and write margins while reducing power consumption. The design operates at 3GHz with a 1.1V power supply.
Keywords :
CMOS memory circuits; SRAM chips; power consumption; power supply circuits; 1.1 V; 3 GHz; 65 nm; 70 MB; CMOS technology; SRAM; cell read; integrated column-based dynamic power supply; multi-V scheme; reduced power consumption; write margins; CMOS technology; Circuits; Design optimization; Interleaved codes; Logic; Power supplies; Random access memory; Stability; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494075
