• DocumentCode
    1673617
  • Title

    0.3 to 1.5V embedded SRAM with device-fluctuation-tolerant access-control and cosmic-ray-immune hidden-ECC scheme

  • Author

    Suzuki, Toshikazu ; Yamagami, Yoshinobu ; Hatanaka, Ichiro ; Shibayama, Akinori ; Akamatsu, Hironori ; Yamauchi, Hiroyuki

  • Author_Institution
    Matusushita, Nagaokakyo, Japan
  • fYear
    2005
  • Firstpage
    484
  • Abstract
    A device-fluctuation-tolerant access-control scheme and a unique cosmic-ray-immune hidden-ECC scheme are implemented in a 32kB SRAM in a 0.13 μm CMOS process. The SRAM operates at 0.3V at 6.8MHz under severe device fluctuations. Operation ranges from 30MHz at 0.4V to 960MHz at 1.5V. The hidden-ECC reduces access-timing and the calculated soft-error-rate is reduced by 3.6×1010 per MB.
  • Keywords
    CMOS memory circuits; SRAM chips; embedded systems; error correction codes; error statistics; 0.13 micron; 0.3 to 1.5 V; 30 to 960 MHz; 32 kB; 6.8 MHz; CMOS process; access timing; cosmic-ray-immune hidden-ECC scheme; device-fluctuation-tolerant access control; embedded SRAM; soft error rate; CMOS technology; Circuits; Cosmic rays; Delay; Error correction codes; Fluctuations; Frequency synchronization; Random access memory; Tail; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1494080
  • Filename
    1494080
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1673617