Power aware cache miss reduction by energy efficient victim retention

Most of the chip-multiprocessors share a large sized last level cache(LLC) which is divided into multiple banks in NUCA based architectures. Recent study on LLC power consumption indicates that, LLC consumes principal amount of chip power. The LLC power consumption can be divided into two major parts: dynamic power and static power. Techniques have been proposed to reduce static power by powering off some less utilized cache portions. But, powering off some cache portion can degrade the system performance. In this paper, we reduce the cache power consumption by shutting down some cache ways of less utilized cache sets and then apply victim retention(VR) technique in the remaining portion to reduce cache misses. Experimental analysis shows 35% reduction in static power and 11.31% reduction in EDP, on an average for a 2MB LLC with negligible change in performance.