DocumentCode
1673644
Title
A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor
Author
Dhong, Sang H. ; Takahashi, Osamu ; White, Michael ; Asano, Toru ; Nakazato, Takaaki ; Silberman, Joel ; Kawasumi, Atsushi ; Yoshihara, Hiroshi
Author_Institution
IBM, Austin, TX, USA
fYear
2005
Firstpage
486
Abstract
A 6-stage fully pipelined embedded SRAM is implemented in a 90nm SOI technology. The array uses a conventional 6-transistor memory cell and sense amplifier to achieve the cycle time while minimizing the impact of device variation. A sum-addressed pre-decoder allows partial activation for power savings.
Keywords
SRAM chips; embedded systems; pipeline processing; power consumption; silicon-on-insulator; 4.8 GHz; 6-transistor memory cell; 90 nm; SOI; cycle time; device variation; fully pipelined embedded SRAM; partial activation; power savings; sense amplifier; streaming processor; sum-addressed pre-decoder; Acceleration; Buffer storage; Decoding; Pipelines; Process design; Random access memory; Read-write memory; Registers; Streaming media; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-8904-2
Type
conf
DOI
10.1109/ISSCC.2005.1494081
Filename
1494081
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