Study on Theory and Key Technologies of Full Digital SPWM Implementation for Three-Level Neutral Point Clamped Inverter

Author

Jian, Liu ; Xianggen, Yin ; Zhe, Zhang ; Qing, Xiong

Author_Institution

Huazhong Univ. of Sci. & Technol., Wuhan

fYear

2007

Firstpage

1287

Lastpage

1291

Abstract

In this paper, the digital realization theory and key technologies of Multi-Level SPWM scheme implementation for the three-level neutral point clamped (NPC) inverter is presented. The digital asymmetrical regular sampling principle of SPWM is realized with only a single FPGA chip LFEC10 from LATTICE Inc. and the programming language is very high speed integrated circuit hardware description language (VHDL). This full digital circuit can provide an effective, flexible, and safe solution for high-power inverts. At last, some simulation and experimental results have been presented and discussed in this paper.

Keywords

PWM invertors; field programmable gate arrays; hardware description languages; integrated circuit design; logic design; very high speed integrated circuits; FPGA chip; VHDL; digital SPWM implementation; digital asymmetrical regular sampling; hardware description language; three-level neutral point clamped inverter; very-high speed integrated circuit; Circuit simulation; Computer languages; Digital circuits; Field programmable gate arrays; Hardware design languages; Integrated circuit technology; Inverters; Lattices; Sampling methods; Very high speed integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Circuits and Systems, 2007. ICCCAS 2007. International Conference on

Conference_Location

Kokura

Print_ISBN

978-1-4244-1473-4

Type

conf

DOI

10.1109/ICCCAS.2007.4348282

Filename

4348282