DocumentCode
1673706
Title
A 3mW 74dB SNR 2MHz CT ΔΣ ADC with a tracking-ADC-quantizer in 0.13 μm CMOS
Author
Dörrer, Lukas ; Kuttner, Franz ; Greco, Patrizia ; Derksen, Sven
Author_Institution
Infineon, Villach, Austria
fYear
2005
Firstpage
492
Abstract
A third-order CT multibit ΔΣ ADC for wireless applications is implemented in 0.13 μm CMOS. Instead of using a 4b flash quantizer, a tracking ADC composed of 3 comparators with interpolation is used to reduce the power consumption. Over a bandwidth of 2MHz the SNR is 74dB. The ADC consumes 3mW from a 1.5V supply when clocked at 104MHz.
Keywords
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); delta-sigma modulation; interpolation; power consumption; 0.13 micron; 1.5 V; 104 MHz; 2 MHz; 3 mW; CMOS; comparators; interpolation; reduced power consumption; third-order CT multibit ΔΣ ADC; tracking ADC; wireless applications; Added delay; Bandwidth; Capacitance; Counting circuits; Energy consumption; Feedforward systems; GSM; Jitter; Linearity; Wireless communication;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-8904-2
Type
conf
DOI
10.1109/ISSCC.2005.1494084
Filename
1494084
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