Partitioning-based test time reduction for core-based 3DICs

To maintain the ever increasing demand for compaction as well as performance, 3D ICs were introduced. They have some additional advantages over their 2D counterparts in various aspects like heterogeneous integration, higher frequency, lesser interconnect length and increased bandwidth. Testing of core-based dies in 3D-SOCs poses many new challenges. This paper describes an automated post-bond core-based 3D SOC testing technique, under constraints on TAM width and number of available TSVs. We have conducted the experiments on the ITC 02 SOC test benchmarks and have compared the test times with that of earlier works to show the efficacy of our algorithm. Our partitioning-based algorithm exhibits much better performance compared to its earlier counterparts.