Title :
A 0.5V filter with PLL-based tuning in 0.18 μm CMOS
Author :
Chatterjee, Shouri ; Tsividis, Yannis ; Kinget, Peter
Author_Institution :
Columbia Univ., New York, NY, USA
Abstract :
Design techniques that allow analog circuit operation with supply voltages as low as 0.5V are presented. A fully integrated 135kHz fifth-order elliptic LPF, including automatic bias circuits and an on-chip PLL for tuning, is implemented with standard devices in a 0.18 μm CMOS process. The 1mm2 chip has a measured DR of 57dB and draws 2.2mA from the 0.5V supply.
Keywords :
CMOS analogue integrated circuits; circuit tuning; elliptic filters; low-pass filters; phase locked loops; 0.18 mm; 0.5 V; 135 kHz; 2.2 mA; CMOS; PLL-based tuning; analog circuit operation; automatic bias circuits; fifth-order elliptic LPF; filter; CMOS technology; Charge pumps; Feedback circuits; Filters; MOS devices; Maintenance; Resistors; Temperature; Threshold voltage; Transconductance;
Conference_Titel :
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-8904-2
DOI :
10.1109/ISSCC.2005.1494091
