DocumentCode :
1674004
Title :
BONY: An algorithm to generate large synthetic combinational benchmark circuits
Author :
Talukdar, Priyankar
Author_Institution :
Int. Inst. of Inf. Technol., Bangalore, China
fYear :
2015
Firstpage :
1
Lastpage :
2
Abstract :
In this paper we address the problem of generating large combinational circuits with good fan in and fanout distribution, high Rent factor and large number of reconvergent gates. Such circuits are in great demand in testing various circuit related algorithms as bench mark circuits or networks. Generation of such circuits is conjectured to be NP Hard problem and available tools are mostly proprietary in nature and may not be available for academic research purposes. In this paper we present a tool for generating large combinational circuits with desirable properties. Our tool generates a netlist that resemble real designs in terms of Rent parameter (interconnect complexity), net degree distribution, path depth and gate counts. We compare the circuits generated by our method with ISCAS-85 benchmark and OpenCores circuits. Using our method, 500K gates combinational circuit is generated in 8 seconds and 1.5 million gates in 36 seconds respectively. We prove that the circuits generated are acyclic in nature.
Keywords :
combinational circuits; computational complexity; optimisation; NP hard problem; gate counts; interconnect complexity; net degree distribution; path depth; synthetic combinational benchmark circuits; Benchmark testing; Combinational circuits; Design automation; Integrated circuit interconnections; Logic gates; Solid modeling; EDA; Synthetic benchmark; circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design and Test (VDAT), 2015 19th International Symposium on
Conference_Location :
Ahmedabad
Print_ISBN :
978-1-4799-1742-6
Type :
conf
DOI :
10.1109/ISVDAT.2015.7208094
Filename :
7208094
Link To Document :
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