Methodology for optimizing ESD protection for high speed LVDS based I/Os

This work explores a methodology to optimize the layout of a electro-static discharge (ESD) structures for improving the performance of low voltage swing differential amplifier (LVDS). The parasitic capacitance of ESD structures are extracted. The role of our work is to optimize the parasitic capacitance in the I/O circuit while improving the ESD robustness. The work first compares impact of capacitance in LVDS swing behaviour and it has been observed that there is a sharp fall due to charging time constant. As ESD robustness improves by increasing the ballasting behaviour while marginal increase in capacitance, there is a much better improvement in width scaling down leads to much reduction in capacitance and thus I/O circuit improvement.