Analysis of stability and different speed boosting assist techniques towards the design and optimization of high speed SRAM cell

Author

Sinha, Rohan ; Samanta, Pranay

Author_Institution

Dept. of Electron. & Commun. Eng., IIIT Delhi, New Delhi, India

fYear

2015

Firstpage

1

Lastpage

6

Abstract

Cell stability with efficient operation are the two major concerns towards the design of SRAM bit cells in sub nanometer CMOS technologies. Supply scaling, intra-die parameter variations are some of the major factors governing the cell stability and controllability. This paper analyses the different stability criteria and the effect of various assist techniques in designing a SRAM cell for high speed operation. The design steps required for proper sizing of the bit cell is also explained in detail. Monte Carlo simulations are done for calculating the six sigma variation of the different stability parameters. The simulations are done in ELDO Spice and the process technology used is 65nm CMOS process.

Keywords

CMOS memory circuits; Monte Carlo methods; SRAM chips; circuit stability; logic design; CMOS process; ELDO Spice; Monte Carlo simulations; SRAM bit cells; assist techniques; cell stability; intra-die parameter variations; sigma variation; stability criteria; stability parameters; sub nanometer CMOS technologies; supply scaling; Logic gates; Monte Carlo methods; Noise; SRAM cells; Stability analysis; Thermal stability; Transistors; BL(Bit line); CR(Cell Ratio); DRV (Data Retention voltage); PR(Pull up ratio); PVT(Process; RNM (Retention Noise Margin); SNM (Static Noise Margin); SRAM; Voltage and Temperature); WL(Word line); WM (Write Margin);

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and Test (VDAT), 2015 19th International Symposium on

Conference_Location

Ahmedabad

Print_ISBN

978-1-4799-1742-6

Type

conf

DOI

10.1109/ISVDAT.2015.7208097

Filename

7208097