Analysis of stability and different speed boosting assist techniques towards the design and optimization of high speed SRAM cell

Cell stability with efficient operation are the two major concerns towards the design of SRAM bit cells in sub nanometer CMOS technologies. Supply scaling, intra-die parameter variations are some of the major factors governing the cell stability and controllability. This paper analyses the different stability criteria and the effect of various assist techniques in designing a SRAM cell for high speed operation. The design steps required for proper sizing of the bit cell is also explained in detail. Monte Carlo simulations are done for calculating the six sigma variation of the different stability parameters. The simulations are done in ELDO Spice and the process technology used is 65nm CMOS process.