Title :
An all-digital frequency locked loop (ADFLL) with a pulse output direct digital frequency synthesizer (DDFS) and an adaptive phase estimator
Author :
Gothandaraman, Akila ; Islam, Syed K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Tennessee Univ., Knoxville, TN, USA
Abstract :
An algorithm for frequency synthesizing all-digital frequency locked loops (ADFLLs) with fast frequency acquisition is presented in this paper. A Pulse Output Direct Digital Frequency Synthesizer (DDFS) with reduced hardware cost and architecture, full digitization, easy design and implementation is proposed. An adaptive phase estimator is also proposed. The DDFS has 16-bit binary weighted control and the simulations show that the ADFLL can operate in the frequency range between 50 MHz and 500 MHz.
Keywords :
adaptive estimation; direct digital synthesis; frequency locked loops; frequency synthesizers; phase estimation; 16 bit; 50 to 500 MHz; adaptive phase estimator; all-digital frequency locked loop; pulse output direct digital frequency synthesizer; Clocks; Frequency estimation; Frequency locked loops; Frequency synthesizers; Logic; Phase estimation; Phase locked loops; Signal processing algorithms; Tuning; Weight control;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE
Print_ISBN :
0-7803-7694-3
DOI :
10.1109/RFIC.2003.1213949
