Clocking and circuit design for a parallel I/O on a first-generation CELL processor

Author

Chang, Ken ; Pamarti, Sudhakar ; Kaviani, Kambiz ; Alon, Elad ; Shi, Xudong ; Chin, T.J. ; Shen, Jie ; Yip, Gary ; Madden, Chris ; Schmitt, Ralf ; Yuan, Chuck ; Assaderaghi, Fari ; Horowitz, Mark

Author_Institution

Rambus, Los Altos, CA, USA

fYear

2005

Firstpage

526

Abstract

A parallel I/O is integrated on a first-generation CELL processor in 90nm SOI CMOS. A clock-tracking architecture suppresses reference jitter to achieve 6.4Gbit/s/link operation at 21.6mW/Gbit/s. SOI effects on analog circuits, in particular high-speed receivers, are addressed to achieve a receiver sensitivity of ±12mV at 6.4Gbit/s with BER <10^-14 measured using 7b PRBS data.

Keywords

CMOS integrated circuits; analogue integrated circuits; clocks; error statistics; receivers; silicon-on-insulator; timing jitter; 21.6 mW; 6.4 Gbit/s; 90 nm; BER; PRBS data; SOI CMOS; analog circuits; circuit design; clock-tracking architecture; clocking; first-generation CELL processor; high-speed receivers; parallel I/O; reference jitter suppression; Aggregates; Application specific integrated circuits; Bandwidth; CMOS process; Circuit synthesis; Clocks; Passband; Phase locked loops; Semiconductor device measurement; Timing jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-8904-2

Type

conf

DOI

10.1109/ISSCC.2005.1494101

Filename

1494101